`timescale 1ns / 1ps

module testbench;
    reg clk;
    reg rst;

    // Instantiate CPU module
    CPU cpu (
            .CLK(clk),
            .RST(rst)
        );

    // Clock generation
    always #5 clk = ~clk;

    // Initial block for simulation setup
    initial begin
        clk = 0;
        rst = 1;

        // Apply reset for a few clock cycles
        #10 rst = 0;

        // Run simulation for a certain period
        #2000 $finish;
    end

endmodule
